Tamp Control Register 3 (Tamp_Cr3) - ST STM32WL5 Series Reference Manual

RM0453
Bit 23 BKERASE: Backup registers
Bits 22:19 Reserved, must be kept at reset value.
Bit 18 TAMP3MSK: Tamper 3 mask
Bit 17 TAMP2MSK: Tamper 2 mask
Bit 16 TAMP1MSK: Tamper 1 mask
Bits 15:3 Reserved, must be kept at reset value.
Bit 2 TAMP3NOER: Tamper 3 no erase
Bit 1 TAMP2NOER: Tamper 2 no erase
Bit 0 TAMP1NOER: Tamper 1 no erase
1. The device secrets erased by tamp_erase signal (refer to
33.6.3

TAMP control register 3 (TAMP_CR3)

Address offset: 0x08
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Writing '1' to this bit reset the backup registers
read as 0.
0: Tamper 3 event generates a trigger event and TAMP3F must be cleared by software to
allow next tamper event detection.
1: Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by
hardware. The backup registers
The tamper 3 interrupt must not be enabled when TAMP3MSK is set.
0: Tamper 2 event generates a trigger event and TAMP2F must be cleared by software to
allow next tamper event detection.
1: Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by
hardware. The backup registers
The tamper 2 interrupt must not be enabled when TAMP2MSK is set.
0: Tamper 1 event generates a trigger event and TAMP1F must be cleared by software to
allow next tamper event detection.
1: Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by
hardware. The backup registers
The tamper 1 interrupt must not be enabled when TAMP1MSK is set.
0: Tamper 3 event erases the backup registers.
1: Tamper 3 event does not erase the backup registers
0: Tamper 2 event erases the backup registers.
1: Tamper 2 event does not erase the backup registers
0: Tamper 1 event erases the backup registers.
1: Tamper 1 event does not erase the backup registers
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. Res. Res.
Tamper and backup registers (TAMP)
(1)
erase
(1)
. Writing 0 has no effect. This bit is always
(1)
are not erased.
(1)
are not erased.
(1)
are not erased.
Table 218: TAMP interconnection).
24 23 22
Res. Res. Res.
8 7 6
ITAMP8 ITAMP6
Res. Res.
NOER NOER
rw
RM0453 Rev 1
(1)
.
(1)
.
(1)
.
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
ITAMP5 ITAMP3
Res.
NOER NOER
rw rw rw
17 16
Res. Res.
1 0
Res. Res.
1049/1461
1057