Timx Event Generation Register (Timx_Egr)(X = 16 To 17) - ST STM32WL5 Series Reference Manual

General-purpose timers (TIM16/TIM17)
Bit 0 UIF: Update interrupt flag
27.4.5

TIMx event generation register (TIMx_EGR)(x = 16 to 17)

Address offset: 0x14
Reset value: 0x0000
15 14 13
Res. Res. Res. Res.
Bits 15:8 Reserved, must be kept at reset value.
Bit 7 BG: Break generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
Bit 6 Reserved, must be kept at reset value.
Bit 5 COMG: Capture/Compare control update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action
1: When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels that have a complementary output.
Bits 4:2 Reserved, must be kept at reset value.
Bit 1 CC1G: Capture/Compare 1 generation
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: A capture/compare event is generated on channel 1:
If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
Bit 0 UG: Update generation
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
1: Reinitialize the counter and generates an update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler ratio is not affected).
934/1461
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are updated:
– At overflow regarding the repetition counter value (update if repetition counter = 0)
and if the UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if
URS=0 and UDIS=0 in the TIMx_CR1 register.
12 11 10 9
Res. Res. Res.
8 7 6
Res. BG Res. COMG
w
RM0453 Rev 1
5 4 3 2
Res. Res. Res.
w
RM0453
1 0
CC1G UG
w w