Table of Contents
Advertisement
Debug support (DBG)
38.4.1
DP identification register (DP_DPIDR)
Address offset: 0x00
Reset value: 0x5BA0 2477
Read only
31
30
29
28
REVISION[3:0]
r
r
r
r
15
14
13
12
VERSION[3:0]
r
r
r
r
Bits 31:28 REVISION[3:0]: revision code
0x5
Bits 27:20 PARTNO[7:0]: part number for the debug port
0xBA
Bits 19:17 Reserved, must be kept at reset value.
Bit 16 MIN: minimal debug port (MINDP) implementation
0x0: MINDP not implemented (transaction counter and pushed operations are supported)
Bits 15:12 VERSION[3:0]: DP architecture version
0x2: DPv2
Bits 11:1 DESIGNER[10:0]: JEDEC designer identity code
0x23B: Arm
Bit 0 Reserved, must be kept at reset value.
38.4.2
DP abort register (DP_ABORTR)
Address offset: 0x00
Reset value: 0x0000 0000
Write only
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
1334/1461
27
26
25
r
r
r
11
10
9
r
r
r
®
JEDEC code
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
21
PARTNO[7:0]
r
r
r
8
7
6
DESIGNER[10:0]
r
r
r
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0453 Rev 1
20
19
18
Res.
Res.
r
r
5
4
3
2
r
r
r
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
ORUN
WD
STK
Res.
ERR
ERR
ERR
CLR
CLR
CLR
w
w
w
RM0453
17
16
Res.
MIN
r
1
0
Res.
r
17
16
Res.
Res.
1
0
STK
DAP
CMP
ABORT
CLR
w
w
Advertisement
Table of Contents
Need help?
Do you have a question about the STM32WL5 Series and is the answer not in the manual?
Questions and answers