Rtc Alarm B Sub Second Register (Rtc_Alrmbssr) - ST STM32WL5 Series Reference Manual

Real-time clock (RTC)
32.6.17

RTC alarm B sub second register (RTC_ALRMBSSR)

This register can be written only when ALRBE is reset in RTC_CR register, or in initialization
mode.
Address offset: 0x4C
Backup domain reset value: 0x0000 0000
System reset: not affected
31 30 29
SSCLR Res. MASKSS[5:4]
rw rw
15 14 13
Res.
rw rw
Bit 31 SSCLR: Clear synchronous counter on alarm (Binary mode only)
Note: SSCLR must be kept to 0 when BCD or mixed mode is used (BIN = 00, 10 or 11).
Bit 30 Reserved, must be kept at reset value.
Bits 29:24 MASKSS[5:0]: Mask the most-significant bits starting at this bit
Note: In BCD mode (BIN=00)The overflow bits of the synchronous counter (bits 15) is never
Bits 23:15
Bits 14:0 SS[14:0]: Sub seconds value
1034/1461
28 27 26 25
MASKSS[3:0]
rw rw rw rw
12 11 10 9
rw rw rw rw
0: The synchronous binary counter (SS[31:0] in RTC_SSR) is free-running.
1: The synchronous binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to
RTC_ALRMBBINR → SS[31:0] value and is automatically reloaded with 0xFFFF FFFF when
reaching RTC_ALRMBBINR → SS[31:0].
0: No comparison on sub seconds for Alarm B. The alarm is set when the seconds unit is
incremented (assuming that the rest of the fields match).
1: SS[31:1] are don't care in Alarm B comparison. Only SS[0] is compared.
2: SS[31:2] are don't care in Alarm B comparison. Only SS[1:0] are compared.
...
31: SS[31] is don't care in Alarm B comparison. Only SS[30:0] are compared.
From 32 to 63: All 32 SS bits are compared and must match to activate alarm.
compared. This bit can be different from 0 only after a shift operation.
Reserved, must be kept at reset value.
This value is compared with the contents of the synchronous prescaler counter to determine
if alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared.
This field is the mirror of SS[14:0] in the RTC_ALRMBBINR, and so can also be read or
written through RTC_ALRMBBINR.
24 23 22
Res. Res.
rw
8 7 6
SS[14:0]
rw rw rw
RM0453 Rev 1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw w
RM0453
17 16
Res. Res.
1 0
rw rw