Figure 307. Configurable Stop Bits - ST STM32WL5 Series Reference Manual

RM0453
Every character is preceded by a start bit which corresponds to a low logic level for one bit
period. The character is terminated by a configurable number of stop bits.
The number of stop bits can be configured to 0.5, 1, 1.5 or 2.
Note: The TE bit must be set before writing the data to be transmitted to the USART_TDR.
The TE bit should not be reset during data transmission. Resetting the TE bit during the
transmission corrupts the data on the TX pin as the baud rate counters get frozen. The
current data being transmitted are then lost.
An idle frame is sent when the TE bit is enabled.
Configurable stop bits
The number of stop bits to be transmitted with every character can be programmed in
USART_CR2, bits 13,12.
•
1 stop bit: This is the default value of number of stop bits.
•
2 stop bits: This is supported by normal USART, Single-wire and Modem modes.
•
1.5 stop bits: To be used in Smartcard mode.
An idle frame transmission includes the stop bits.
A break transmission features 10 low bits (when M[1:0] = '00') or 11 low bits (when
M[1:0] = '01') or 9 low bits (when M[1:0] = '10') followed by 2 stop bits (see
not possible to transmit long breaks (break of length greater than 9/10/11 low bits).
CLOCK
Universal synchronous/asynchronous receiver transmitter (USART/UART)

Figure 307. Configurable stop bits

Data frame
Start bit Bit0 Bit1 Bit2
8-bit data, 1 1/2 Stop bits
Data frame
Start bit Bit0 Bit1 Bit2
8-bit data, 2 Stop bits
Data frame
Start bit Bit0 Bit1 Bit2
RM0453 Rev 1
8-bit data, 1 Stop bit
Possible
parity bit
Bit3 Bit4 Bit5 Bit6
Possible
parity bit
Bit3 Bit4 Bit5 Bit6
Possible
parity bit
Bit3 Bit4 Bit5 Bit6
Figure
Next
Next data frame
start
Stop
Bit7
bit
bit
**
** LBCL bit controls last data clock pulse
Next
Next data frame
start
Bit7 1.5
bit
Stop
bits
Next
Next data frame
start
2
Bit7
bit
Stop
bits
307). It is
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