Table of Contents
Advertisement
RM0453
Figure 244. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Auto-reload preload
Figure 245. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Auto-reload preload
Auto-reload shadow
Write a new value in TIMx_ARR
CK_PSC
CEN
31
(UIF)
FF
register
Write a new value in TIMx_ARR
CK_PSC
CEN
F0
(UIF)
F5
register
register
RM0453 Rev 1
General-purpose timers (TIM16/TIM17)
preloaded)
32
33
34
35
36
00
preloaded)
F1 F2
F3 F4 F5
00
F5
01
02
03
04
05 06 07
36
01
02
03
04
05 06 07
36
36
MS31082V2
MS31083V2
909/1461
952
Advertisement
Table of Contents
Need help?
Do you have a question about the STM32WL5 Series and is the answer not in the manual?
Questions and answers