ST STM32WL5 Series Reference Manual page 1202

Universal synchronous/asynchronous receiver transmitter (USART/UART)
Bit 5 RXFNE: RXFIFO not empty
Bit 4 IDLE: Idle line detected
Note: The IDLE bit is not set again until the RXFNE bit has been set (i.e. a new idle line
Bit 3 ORE: Overrun error
Note: When this bit is set, the USART_RDR register content is not lost but the shift register is
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RXFNE bit is set by hardware when the RXFIFO is not empty, meaning that data can be
read from the USART_RDR register. Every read operation from the USART_RDR frees a
location in the RXFIFO.
RXFNE is cleared when the RXFIFO is empty. The RXFNE flag can also be cleared by
writing 1 to the RXFRQ in the USART_RQR register.
An interrupt is generated if RXFNEIE = 1 in the USART_CR1 register.
0: Data is not received
1: Received data is ready to be read.
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if
IDLEIE = 1 in the USART_CR1 register. It is cleared by software, writing 1 to the IDLECF in
the USART_ICR register.
0: No Idle line is detected
1: Idle line is detected
occurs).
If Mute mode is enabled (MME = 1), IDLE is set if the USART is not mute (RWU = 0),
whatever the Mute mode selected by the WAKE bit. If RWU = 1, IDLE is not set.
This bit is set by hardware when the data currently being received in the shift register is
ready to be transferred into the USART_RDR register while RXFF = 1. It is cleared by a
software, writing 1 to the ORECF, in the USART_ICR register.
An interrupt is generated if RXFNEIE = 1 or EIE = 1 in the USART_CR1 register.
0: No overrun error
1: Overrun error is detected
overwritten. An interrupt is generated if the ORE flag is set during multi buffer
communication if the EIE bit is set.
This bit is permanently forced to 0 (no overrun detection) when the bit OVRDIS is set in
the USART_CR3 register.
RM0453 Rev 1
RM0453