Dac Low-Power Modes; Table 117. Effect Of Low-Power Modes On Dac - ST STM32WL5 Series Reference Manual

Digital-to-analog converter (DAC)
Independent trigger with single LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
1. Set the DAC channel trigger enable bit, TEN1.
2. Configure the trigger sources by setting different values in the TSEL1[3:0] bits.
3. Configure the DAC channel WAVE1[1:0] bits as 01 and the same LFSR mask value in
the MAMP1[3:0] bits.
4. Load the DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel trigger arrives, the LFSR1 counter, with the same mask, is added to
the DHR1 register and the sum is transferred into DAC_DOR1 (three dac_pclk clock cycles
later). Then the LFSR1 counter is updated.
Independent trigger with single triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
1. Set the DAC channel trigger enable bits, TEN1.
2. Configure the trigger sources by setting different values in the TSEL1[3:0] bits.
3. Configure the DAC channel WAVE1[1:0] bits as 1x and the same maximum amplitude
value in the MAMP1[3:0] bits.
4. Load the DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a DAC channel trigger arrives, the DAC channel triangle counter, with the same
triangle amplitude, is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three dac_pclk clock cycles later). The DAC channel triangle counter is then
updated.
Independent trigger with single sawtooth generation
To configure the DAC in this conversion mode, the following sequence is required:
1. Configure the trigger sources by setting different values in STRSTTRIGSEL1[3:0] and
STINCTRIGSEL1[3:0] bits.
2. Configure the DAC channel WAVE1[1:0] bits to 11 and set the same
STRSTDATA1[11:0], STINCDATA1[15:0] and STDIR1 values for each register.
When a DAC channel trigger arrives, the DAC channel sawtooth counter updates the DHR1
register and transfers it into DAC_DOR1 (three APB clock cycles later).
19.5

DAC low-power modes

Sleep
LPRun
LPSleep
606/1461

Table 117. Effect of low-power modes on DAC

Mode
No effect, DAC used with DMA
No effect.
No effect. DAC used with DMA.
Description
RM0453 Rev 1
RM0453