Usart Multiprocessor Communication - ST STM32WL5 Series Reference Manual

Universal synchronous/asynchronous receiver transmitter (USART/UART)
35.5.10

USART multiprocessor communication

It is possible to perform USART multiprocessor communications (with several USARTs
connected in a network). For instance one of the USARTs can be the master with its TX
output connected to the RX inputs of the other USARTs, while the others are slaves with
their respective TX outputs logically ANDed together and connected to the RX input of the
master.
In multiprocessor configurations, it is often desirable that only the intended message
recipient actively receives the full message contents, thus reducing redundant USART
service overhead for all non addressed receivers.
The non-addressed devices can be placed in Mute mode by means of the muting function.
To use the Mute mode feature, the MME bit must be set in the USART_CR1 register.
Note: When FIFO management is enabled and MME is already set, MME bit must not be cleared
and then set again quickly (within two usart_ker_ck cycles), otherwise Mute mode might
remain active.
When the Mute mode is enabled:
•
none of the reception status bits can be set;
•
all the receive interrupts are inhibited;
•
the RWU bit in USART_ISR register is set to '1'. RWU can be controlled automatically
by hardware or by software, through the MMRQ bit in the USART_RQR register, under
certain conditions.
The USART can enter or exit from Mute mode using one of two methods, depending on the
WAKE bit in the USART_CR1 register:
•
Idle Line detection if the WAKE bit is reset,
•
Address Mark detection if the WAKE bit is set.
Idle line detection (WAKE = 0)
The USART enters Mute mode when the MMRQ bit is written to '1' and the RWU is
automatically set.
The USART wakes up when an Idle frame is detected. The RWU bit is then cleared by
hardware but the IDLE bit is not set in the USART_ISR register. An example of Mute mode
behavior using Idle line detection is given in
1150/1461
Figure 313.
RM0453 Rev 1
RM0453