Table of Contents
Advertisement
Debug support (DBG)
CTI CoreSight peripheral identity register 0 (CTI_PIDR0)
Address offset: 0xFE0
Reset value: 0x0000 0006
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PARTNUM[7:0]: part number bits [7:0]
0x06: CTI part number
CTI CoreSight peripheral identity register 1 (CTI_PIDR1)
Address offset: 0xFE4
Reset value: 0x0000 00B9
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 JEP106ID[3:0]: JEP106 identity code bits [3:0]
0xB: Arm
Bits 3:0 PARTNUM[11:8]: part number bits [11:8]
0x9: CTI part number
1378/1461
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
®
JEDEC code
RM0453 Rev 1
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
PARTNUM[7:0]
r
r
r
r
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
JEP106ID[3:0]
r
r
r
r
RM0453
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
r
r
r
r
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
PARTNUM[11:8]
r
r
r
r
Advertisement
Table of Contents
Need help?
Do you have a question about the STM32WL5 Series and is the answer not in the manual?
Questions and answers