Figure 240. Counter Timing Diagram, Internal Clock Divided By 1; Figure 241. Counter Timing Diagram, Internal Clock Divided By 2 - ST STM32WL5 Series Reference Manual

RM0453
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Timerclock = CK_CNT
Counter register
Counter overflow
Update event (UEV)
Update interrupt flag

Figure 240. Counter timing diagram, internal clock divided by 1

CK_PSC
CNT_EN
31
(UIF)

Figure 241. Counter timing diagram, internal clock divided by 2

CK_PSC
CNT_EN
0034
(UIF)
RM0453 Rev 1
General-purpose timers (TIM16/TIM17)
32 33 34 35 36 00
0036
0035
01 02 03
04 05
0000 0002
0001
06 07
MS31078V2
0003
MS31079V2
907/1461
952