Tpiu Supported Port Size Register (Tpiu_Sspsr); Tpiu Current Port Size Register (Tpiu_Cspsr); Figure 391. Tpiu Architecture - ST STM32WL5 Series Reference Manual

Debug support (DBG)
ITM ATB
For more information on the TPIU, refer to the Arm
Reference Manual [2.].
38.11.1

TPIU supported port size register (TPIU_SSPSR)

Address offset: 0x000
Reset value: 0x0000 000F
31 30 29 28
r r r
15 14 13 12
r r r
Bits 31:0 PORTSIZE[31:0]: supported trace port sizes, from 1 to 32 pins
Bit n-1 when set indicates that port size n is supported.
0x0000 000F: Port sizes 1 to 4 supported
38.11.2

TPIU current port size register (TPIU_CSPSR)

Address offset: 0x004
Reset value: 0x0000 0001
31 30 29 28
rw rw rw rw
15 14 13 12
rw rw rw rw
Bits 31:0 PORTSIZE[31:0]: current trace port size
Bit n-1 when set indicates that the current port size is n pins. The value of n must be within
the range of supported port sizes (1-4). Only one bit can be set, or unpredictable behaviour
may result. This register must be modified only when the formatter is stopped.
1408/1461

Figure 391. TPIU architecture

ATB
interface
APB
PPB
interface
27 26 25
r r r r
11 10 9
r r r r
27 26 25
rw rw rw
11 10 9
rw rw rw
TPIU
Trace
Formatter output
(serializer)
®
CoreSight™ SoC-400 Technical
24 23 22
PORTSIZE[31:16]
r r r
8 7 6
PORTSIZE[15:0]
r r r
24 23 22
PORTSIZE[31:16]
rw rw rw
8 7 6
PORTSIZE[15:0]
rw rw rw
RM0453 Rev 1
TRACESWO
21 20 19 18
r r r r
5 4 3 2
r r r r
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0453
MSv60741V1
17 16
r r
1 0
r r
17 16
rw rw
1 0
rw rw