I2C Timing Register (I2C_Timingr) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Inter-integrated circuit (I2C) interface
34.7.5

I2C timing register (I2C_TIMINGR)

Address offset: 0x10
Reset value: 0x0000 0000
Access: No wait states
31
30
29
28
PRESC[3:0]
rw
rw
rw
rw
15
14
13
12
SCLH[7:0]
rw
rw
rw
rw
Bits 31:28 PRESC[3:0]: Timing prescaler
Bits 27:24 Reserved, must be kept at reset value.
Bits 23:20 SCLDEL[3:0]: Data setup time
Note: t
Bits 19:16 SDADEL[3:0]: Data hold time
Note: SDADEL is used to generate t
Bits 15:8 SCLH[7:0]: SCL high period (master mode)
Note: SCLH is also used to generate t
Bits 7:0 SCLL[7:0]: SCL low period (master mode)
Note: SCLL is also used to generate t
Note:
This register must be configured when the I2C is disabled (PE = 0).
Note:
The STM32CubeMX tool calculates and provides the I2C_TIMINGR content in the I2C
Configuration window.
1118/1461
27
26
25
Res.
Res.
Res.
11
10
9
rw
rw
rw
This field is used to prescale I2CCLK in order to generate the clock period t
data setup and hold counters (refer to
level counters (refer to
I2C master initialization on page
t
= (PRESC+1) x t
PRESC
This field is used to generate a delay t
master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during
t
.
SCLDEL
t
= (SCLDEL+1) x t
SCLDEL
is used to generate t
SCLDEL
This field is used to generate the delay t
master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during
t
.
SDADEL
t
= SDADEL x t
SDADEL
PRESC
This field is used to generate the SCL high period in master mode.
t
= (SCLH+1) x t
SCLH
PRESC
This field is used to generate the SCL low period in master mode.
t
= (SCLL+1) x t
SCLL
PRESC
24
23
22
Res.
SCLDEL[3:0]
rw
rw
8
7
6
rw
rw
rw
I2C timings on page
I2CCLK
between SDA edge and SCL rising edge. In
SCLDEL
PRESC
timing.
SU:DAT
between SCL falling edge and SDA edge. In
SDADEL
timing.
HD:DAT
and t
SU:STO
and t
BUF
SU:STA
RM0453 Rev 1
21
20
19
18
SDADEL[3:0]
rw
rw
rw
rw
5
4
3
2
SCLL[7:0]
rw
rw
rw
rw
1064) and for SCL high and low
1079).
timing.
HD:STA
timings.
RM0453
17
16
rw
rw
1
0
rw
rw
used for
PRESC

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