Lpuart Receiver - ST STM32WL5 Series Reference Manual

RM0453
Idle preamble
TX line
TXE flag
LPUART_DR
F1
TC flag
Software
Software waits until TXE=1
enables the
and writes F2 into DR
LPUART
Software waits until TXE=1
and writes F1 into DR
Note: When FIFO management is enabled, the TXFNF flag is used for data transmission.
Break characters
Setting the SBKRQ bit transmits a break character. The break frame length depends on the
M bits (see
If a '1' is written to the SBKRQ bit, a break character is sent on the TX line after completing
the current character transmission. The SBKF bit is set by the write operation and it is reset
by hardware when the break character is completed (during the stop bits after the break
character). The LPUART inserts a logic 1 signal (STOP) for the duration of 2 bits at the end
of the break frame to guarantee the recognition of the start bit of the next frame.
When the SBKRQ bit is set, the break character is sent at the end of the current
transmission.
When FIFO mode is enabled, sending the break character has priority on sending data even
if the TXFIFO is full.
Idle characters
Setting the TE bit drives the LPUART to send an idle frame before the first data frame.
36.4.6

LPUART receiver

The LPUART can receive data words of either 7 or 8 or 9 bits depending on the M bits in the
LPUART_CR1 register.
Start bit detection
In the LPUART, the start bit is detected when a falling edge occurs on the Rx line, followed
by a sample taken in the middle of the start bit to confirm that it is still '0'. If the start sample
is at '1', then the noise error flag (NE) is set, then the start bit is discarded and the receiver
waits for a new start bit. Else, the receiver continues to sample all incoming bits normally.
Low-power universal asynchronous receiver transmitter (LPUART)
Figure 335. TC/TXE behavior when transmitting
Frame 1
Set by hardware
cleared by software
F2
Software waits until
TXE=1 and writes
F3 into DR
Figure 333).
RM0453 Rev 1
Frame 2
Set by hardware
cleared by software
F3
TC is not set TC is not set
because TXE=0 because TXE=0
Software waits until TC=1
Frame 3
Set by hardware
Set by hardware
TC is set
because TXE=1
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