Cpu1 Breakpoint Unit (Fpb); Fpb Control Register (Fpb_Ctrlr) - ST STM32WL5 Series Reference Manual

Debug support (DBG)
Table 278. CPU1 ROM table register map and reset values (continued)
Offset Register name
ROM_CIDR3
0xFFC
Reset value
Refer to
38.9

CPU1 breakpoint unit (FPB)

The FPB allows the user to set hardware breakpoints. It contains six comparators that
monitor the instruction fetch address and two literal address comparators.
If a match occurs, the address is remapped to an address in system memory, defined by the
FPB_REMAPR register plus an offset corresponding to the matching comparator.
Alternatively, the instruction comparators can be configured to generate a breakpoint
instruction.
38.9.1

FPB control register (FPB_CTRLR)

Address offset: 0x000
Reset value: 0x0000 0260
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
NUM_ NUM_
NUM_
Res. CODE CODE
CODE
5 4
6
r r
Bits 31:15 Reserved, must be kept at reset value.
Bits 11:8 NUM_LIT[3:0]: number of literal address comparators supported (read only)
0x2: Two literal comparators supported.
Bits 14, 13, 12, 7, 6, NUM_CODE[6:0]: number of instruction address comparators supported - least significant bits
5, 4 (read only)
0x6: 6 instruction comparators supported
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 KEY: write protect key
A write to FPB_CTRLR register is ignored if this bit is not set to 1.
Bit 0 ENABLE: FPB enable
0: Disabled
1: Enabled
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Section 38.8: CPU1 ROM table
27 26 25
Res. Res. Res.
11 10 9
NUM_LIT[3:0]
r r r r
for the register boundary addresses.
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
NUM_CODE[3:0]
r r r r
RM0453 Rev 1
PREAMBLE[27:20]
1 0 1 1
20 19 18 17
Res. Res. Res. Res.
4 3 2 1
Res. Res.
KEY
r rw
RM0453
0 0 0 1
16
Res.
0
ENABLE
rw