Tamp Interrupt Enable Register (Tamp_Ier) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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RM0453
Bits 6:5 TAMPPRCH[1:0]: TAMP_INx precharge duration
Bits 4:3 TAMPFLT[1:0]: TAMP_INx filter count
Bits 2:0 TAMPFREQ[2:0]: Tamper sampling frequency
Note:
This register concerns only the tamper inputs in passive mode.
33.6.5

TAMP interrupt enable register (TAMP_IER)

Address offset: 0x2C
Backup domain reset value: 0x0000 0000
System reset: not affected
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 ITAMP8IE: Internal tamper 8 interrupt enable
Bit 22 Reserved, must be kept at reset value.
These bit determines the duration of time during which the pull-up/is activated before each
sample. TAMPPRCH is valid for each of the TAMP_INx inputs.
0x0: 1 RTCCLK cycle
0x1: 2 RTCCLK cycles
0x2: 4 RTCCLK cycles
0x3: 8 RTCCLK cycles
These bits determines the number of consecutive samples at the specified level
(TAMP*TRG) needed to activate a tamper event. TAMPFLT is valid for each of the
TAMP_INx inputs.
0x0: Tamper event is activated on edge of TAMP_INx input transitions to the active level (no
internal pull-up on TAMP_INx input).
0x1: Tamper event is activated after 2 consecutive samples at the active level.
0x2: Tamper event is activated after 4 consecutive samples at the active level.
0x3: Tamper event is activated after 8 consecutive samples at the active level.
Determines the frequency at which each of the TAMP_INx inputs are sampled.
0x0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz)
0x1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz)
0x2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz)
0x3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz)
0x4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz)
0x5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz)
0x6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz)
0x7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
0: Internal tamper 8 interrupt disabled.
1: Internal tamper 8 interrupt enabled.
Tamper and backup registers (TAMP)
24
23
22
ITAMP8
ITAMP6
Res.
Res.
IE
rw
8
7
6
Res.
Res.
Res.
RM0453 Rev 1
21
20
19
18
ITAMP5
ITAMP3
Res.
IE
IE
IE
rw
rw
rw
5
4
3
2
TAMP
Res.
Res.
Res.
3IE
rw
17
16
Res.
Res.
1
0
TAMP
TAMP
2IE
1IE
rw
rw
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