ST STM32WL5 Series Reference Manual page 1374

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Debug support (DBG)
CTI claim tag set register (CTI_CLAIMSETR)
Address offset: 0xFA0
Reset value: 0x0000 000F
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 CLAIMSET[3:0]: claim tag bits setting
Write:
0000: No effect
XXX1: Sets bit 0.
XX1X: Sets bit 1.
X1XX: Sets bit 2.
1XXX: Sets bit 3.
Read:
1111: Indicates there are four bits in claim tag.
CTI claim tag clear register (CTI_CLAIMCLR)
Address offset: 0xFA4
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:4 Reserved, must be kept at reset value.
Bits 3:0 CLAIMCLR[3:0]: claim tag bits reset
Write:
0b0000: No effect
XXX1: Clears bit 0.
XX1X: Clears bit 1.
X1XX: Clears bit 2.
1XXX: Clears bit 3.
Read: Returns current value of claim tag.
1374/1461
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0453 Rev 1
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
Res.
Res.
Res.
Res.
RM0453
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
CLAIMSET[3:0]
rw
rw
rw
rw
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
CLAIMCLR[3:0]
rw
rw
rw
rw

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