Syscfg Cpu1 Interrupt Mask Register 1 (Syscfg_Imr1) - ST STM32WL5 Series Reference Manual

RM0453
11.2.11

SYSCFG CPU1 interrupt mask register 1 (SYSCFG_IMR1)

Address offset: 0x100
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
Res. Res. Res. Res.
Bit 31 EXTI15IM: EXTI15 interrupt mask to CPU1
0: EXTI15 interrupt forwarded to CPU1
1. EXTI15 interrupt to CPU1 masked
Bit 30 EXTI14IM: EXTI14 interrupt mask to CPU1
Bit 29 EXTI13IM: EXTI13 interrupt mask to CPU1
Bit 28 EXTI12IM: EXTI12 interrupt mask to CPU1
Bit 27 EXTI11IM: EXTI11 interrupt mask to CPU1
Bit 26 EXTI10IM: EXTI10 interrupt mask to CPU1
Bit 25 EXTI9IM: EXTI9 interrupt mask to CPU1
Bit 24 EXTI8IM: EXTI8 interrupt mask to CPU1
Bit 23 EXTI7IM: EXTI7 interrupt mask to CPU1
Bit 22 EXTI6IM: EXTI6 interrupt mask to CPU1
Bit 21 EXTI5IM: EXTI5 interrupt mask to CPU1
Bits 20:3 Reserved, must be kept at reset value.
Bit 2 RTCSSRUIM: RTC SSRU interrupt mask to CPU1
0: RTC SSRU interrupt forwarded to CPU1
1. RTC SSRU interrupt to CPU1 masked
Bit 1 Reserved, must be kept at reset value.
Bit 0 RTCSTAMPTAMPLSECSSIM: RTCSTAMPTAMPLSECSS interrupt mask to CPU1
0: RTCSTAMPTAMPLSECSS interrupt forwarded to CPU1
1. RTCSTAMPTAMPLSECSS interrupt to CPU1 masked
28 27 26 25
rw rw rw rw
12 11 10 9
Res. Res. Res.
System configuration controller (SYSCFG)
24 23 22
rw rw rw
8 7 6
Res. Res. Res.
RM0453 Rev 1
21 20 19 18
Res. Res. Res.
rw
5 4 3 2
Res. Res. Res.
rw
17 16
Res. Res.
1 0
Res.
rw
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