Cpu1 Trace Port Interface Unit (Tpiu) - ST STM32WL5 Series Reference Manual

RM0453
Table 280. CPU1 ITM register map and reset values (continued)
Offset Register name
0xE04 to
Reserved
0xE4C
ITM_TCR
0xE80
Reset value
0xE84 to
Reserved
0xFCC
ITM_PIDR4
0xFD0
Reset value
0xFD4 to
Reserved
0xFDC
ITM_PIDR0
0xFE0
Reset value
ITM_PIDR1
0xFE4
Reset value
ITM_PIDR2
0xFE8
Reset value
ITM_PIDR3
0xFEC
Reset value
ITM_CIDR0
0xFF0
Reset value
ITM_CIDR1
0xFF4
Reset value
ITM_CIDR2
0xFF8
Reset value
ITM_CIDR3
0xFFC
Reset value
Refer to
38.11

CPU1 trace port interface unit (TPIU)

The TPIU formats the trace stream and outputs it on the external trace port signals. The
TPIU has one ATB slave ports for incoming trace data from the ITM. The trace port is the
serial-wire output, TRACESWO.
Figure 391
Section 38.8: CPU1 ROM table
shows the TPIU architecture.
Reserved.
TRACEBUSID[6:0]
0 0 0 0 0 0 0 0
Reserved.
Reserved.
for the register boundary addresses.
RM0453 Rev 1
Debug support (DBG)
0 0 0 0 0 0 0
F4KCOUNT JEP106CON
[3:0] [3:0]
0 0 0 0 0 1 0 0
PARTNUM[7:0]
0 0 0 0 0 0 0 1
JEP106ID PARTNUM
[3:0] [11:8]
1 0 1 1 0 0 0 0
REVISION JEP106ID
[3:0] [6:4]
0 0 1 1 1 0 1 1
REVAND[3:0] CMOD[3:0]
0 0 0 0 0 0 0 0
PREAMBLE[7:0]
0 0 0 0 1 1 0 1
PREAMBLE
CLASS[3:0]
[11:8]
1 1 1 0 0 0 0 0
PREAMBLE[19:12]
0 0 0 0 0 1 0 1
PREAMBLE[27:20]
1 0 1 1 0 0 0 1
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