ST STM32WL5 Series Reference Manual page 1140

Universal synchronous/asynchronous receiver transmitter (USART/UART)
Character reception
During an USART reception, data are shifted out least significant bit first (default
configuration) through the RX pin.
Character reception procedure
To receive a character, follow the sequence below:
1. Program the M bits in USART_CR1 to define the word length.
2. Select the desired baud rate using the baud rate register USART_BRR
3. Program the number of stop bits in USART_CR2.
4. Enable the USART by writing the UE bit in USART_CR1 register to '1'.
5. Select DMA enable (DMAR) in USART_CR3 if multibuffer communication is to take
place. Configure the DMA register as explained in
multiprocessor
6. Set the RE bit USART_CR1. This enables the receiver which begins searching for a
start bit.
When a character is received:
•
When FIFO mode is disabled, the RXNE bit is set to indicate that the content of the
shift register is transferred to the RDR. In other words, data have been received and
can be read (as well as their associated error flags).
•
When FIFO mode is enabled, the RXFNE bit is set to indicate that the RXFIFO is not
empty. Reading the USART_RDR returns the oldest data entered in the RXFIFO.
When a data is received, it is stored in the RXFIFO together with the corresponding
error bits.
•
An interrupt is generated if the RXNEIE (RXFNEIE when FIFO mode is enabled) bit is
set.
•
The error flags can be set if a frame error, noise, parity or an overrun error was
detected during reception.
•
In multibuffer communication mode:
–
–
•
In single buffer mode:
–
–
1140/1461
communication.
When FIFO mode is disabled, the RXNE flag is set after every byte reception. It is
cleared when the DMA reads the Receive data Register.
When FIFO mode is enabled, the RXFNE flag is set when the RXFIFO is not
empty. After every DMA request, a data is retrieved from the RXFIFO. A DMA
request is triggered when the RXFIFO is not empty i.e. when there are data to be
read from the RXFIFO.
When FIFO mode is disabled, clearing the RXNE flag is done by performing a
software read from the USART_RDR register. The RXNE flag can also be cleared
by programming RXFRQ bit to '1' in the USART_RQR register. The RXNE flag
must be cleared before the end of the reception of the next character to avoid an
overrun error.
When FIFO mode is enabled, the RXFNE is set when the RXFIFO is not empty.
After every read operation from USART_RDR, a data is retrieved from the
RXFIFO. When the RXFIFO is empty, the RXFNE flag is cleared. The RXFNE flag
can also be cleared by programming RXFRQ bit to '1' in USART_RQR. When the
RXFIFO is full, the first entry in the RXFIFO must be read before the end of the
reception of the next character, to avoid an overrun error. The RXFNE flag
generates an interrupt if the RXFNEIE bit is set. Alternatively, interrupts can be
RM0453 Rev 1
Section 35.5.10: USART
RM0453