Pka Status Register (Pka_Sr) - ST STM32WL5 Series Reference Manual

Public key accelerator (PKA)
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 START: start the operation
Writing 1 to this bit starts the operation which is selected by MODE[5:0], using the operands
and data already written to the PKA RAM. This bit is always read as 0.
Note: START is ignored if PKA is busy.
Bit 0 EN: PKA enable.
0: Disable PKA
1: Enable PKA
Note: When EN=0 PKA RAM can still be accessed by the application.
24.7.2

PKA status register (PKA_SR)

Address offset: 0x04
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 ADDRERRF: Address error flag
0: No Address error
1: Address access is out of range (unmapped address)
This bit is cleared using ADDRERRFC bit in PKA_CLRFR.
Bit 19 RAMERRF: PKA RAM error flag
0: No PKA RAM access error
1: An AHB access to the PKA RAM occurred while the PKA core was computing and using its
internal RAM (AHB PKA_RAM access are not allowed while PKA operation is in progress).
This bit is cleared using RAMERRFC bit in PKA_CLRFR.
Bit 18 Reserved, must be kept at reset value.
Bit 17 PROCENDF: PKA End of Operation flag
0: Operation in progress
1: PKA operation is completed. This flag is set when the BUSY bit is deasserted.
Bit 16 BUSY: PKA operation is in progress
This bit is set to 1 whenever START bit in the PKA_CR is set. It is automatically cleared when the
computation is complete, meaning that PKA RAM can be safely accessed and a new operation can
be started.
0: No operation is in progress (default)
1: An operation is in progress
If PKA is started with a wrong opcode the peripheral is busy for a couple of cycles, then it aborts
automatically the operation and go back to ready (BUSY bit is set to 0).
Bits 15:0 Reserved, must be kept at reset value.
726/1461
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
Res. Res. Res. Res.
RM0453 Rev 1
23 22 21 20
ADDR
Res. Res. Res.
ERRF
r
7 6 5 4
Res. Res. Res. Res.
RM0453
19 18 17
RAM PROC
Res. BUSY
ERRF ENDF
r r
3 2 1
Res. Res. Res. Res.
16
r
0