ST STM32WL5 Series Reference Manual page 855

RM0453
Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to
mode on page
In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else
it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in
TIMx_ARR, then ocxref is held at 100%. PWM is not possible in this mode.
PWM center-aligned mode
Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
'00 (all the remaining configurations having the same effect on the ocxref/OCx signals). The
compare flag is set when the counter counts up, when it counts down or both when it counts
up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
Center-aligned mode (up/down counting) on page
Figure 219
•
TIMx_ARR=8,
• PWM mode is the PWM mode 1,
•
The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.
837.
shows some center-aligned PWM waveforms in an example where:
RM0453 Rev 1
General-purpose timer (TIM2)
840.
Downcounting
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901