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RM0453
Bits 6:4 EXTI13[2:0]: EXTI13 configuration bits
These bits are written by software to select the source input for the EXTI13 external interrupt.
000: PA13 pin
001: PB13 pin
010: PC13 pin
011: Reserved
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 EXTI12[2:0]: EXTI12 configuration bits
These bits are written by software to select the source input for the EXTI12 external interrupt.
000: PA12 pin
001: PB12 pin
010: Reserved
011: Reserved
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Note:
Some of the I/O pins mentioned in this register may not be available on small packages.
11.2.7
SYSCFG SRAM control and status register (SYSCFG_SCSR)
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:9 Reserved, must be kept at reset value.
Bit 8 PKASRAMBSY: PKA SRAM busy by erase operation
0: No PKA SRAM erase operation is ongoing.
1: PKA SRAM erase operation is ongoing.
See
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
Section 2.4: SRAM erase
System configuration controller (SYSCFG)
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
r
for more information on SRAM erase conditions
RM0453 Rev 1
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
Res.
Res.
1
0
r
rw
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