Dwt Coresight Component Identity Register 0 (Dwt_Cidr0); Dwt Coresight Peripheral Identity Register 1 (Dwt_Cidr1) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Debug support (DBG)
38.6.17

DWT CoreSight component identity register 0 (DWT_CIDR0)

Address offset: 0xFF0
Reset value: 0x0000 000D
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[7:0]: component ID bits [7:0]
0x0D: Common ID value
38.6.18

DWT CoreSight peripheral identity register 1 (DWT_CIDR1)

Address offset: 0xFF4
Reset value: 0x0000 00E0
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 CLASS[3:0]: component ID bits [15:12] - component class
0xE: Trace generator component
Bits 3:0 PREAMBLE[11:8]: component ID bits [11:8]
0x0: Common ID value
1360/1461
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0453 Rev 1
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
PREAMBLE[7:0]
r
r
r
r
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
CLASS[3:0]
r
r
r
r
RM0453
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
r
r
r
r
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
PREAMBLE[11:8]
r
r
r
r

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