Figure 128. Advanced-Control Timer Block Diagram - ST STM32WL5 Series Reference Manual

RM0453
TIMx_ETR
On-chip ETR
sources
XOR
TI1[0]
TIMx_CH1
TI1[1..15]
TI2[0]
TIMx_CH2
TI2[1..15]
TI3[0]
TIMx_CH3
TI3[1..15]
TI4[0]
TIMx_CH4
TI4[1..15]
Internal
sources
TIMx_BKIN
TIMx_BKIN2
Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit
Event
Interrupt & DMA output
1. The internal break event source can be:
- A clock failure event generated by CSS. For further information on the CSS, refer to
system on HSE32 (CSS)
- A PVD output
- SRAM parity error signal
®
- Cortex -M4 LOCKUP (Hardfault) output.
- COMPx output, x = 1,2.

Figure 128. Advanced-control timer block diagram

Internal clock (CK_INT)
from RCC
ETRP
Polarity selection &
ETR
edgedetector & prescaler
ITR[0..15]
TI1F_ED
CK_PSC
prescaler
Input
TI1
TI1FP1
filter &
IC1
TI1FP2
Prescaler
edge
detector
TRC
Input
TI2FP1
IC2
filter &
TI2
TI2FP2
Prescaler
edge
TRC
detector
Input
TI3FP3
filter &
TI3
IC3
TI3FP4
Prescaler
edge
detector
TRC
Input
TI4FP3
filter &
IC4
TI4
TI4FP4
Prescaler
edge
TRC
detector
SBIF
Break and Break2 circuitry (1)
ETRF
Input
filter
TRG
ITR
TRC TRGI
TI1FP1
TI2FP2
U
Auto-reload register
Stop, clear or up/down
PSC CK_CNT
+/-
CNT counter
CC1I
U
IC1PS
Capture/Compare 1 register
CC2I
U
IC2PS
Capture/Compare 2 register
CC3I
U
IC3PS
Capture/Compare 3 register
CC4I
U
IC4PS
Capture/Compare 4 register
Capture/Compare 5 register
Capture/Compare 6 register
ETRF
BIF
BRK request
B2IF
BRK2 request
RM0453 Rev 1
Advanced-control timer (TIM1)
Trigger
TRGO
controller
to other timers
to peripherals
Slave
Reset, enable, up/down, count
controller
mode
Encoder
Interface
REP register
Repetition
counter
DTG registers
CC1I
OC1REF
Output
DTG
control
CC2I
Output
OC2REF
control
DTG
CC3I
OC3REF
Output
DTG
control
CC4I
Output
OC4REF
control
Output
OC5REF
control
Output
OC6REF
control
Section 7.2.10: Clock security
UI
U
TIMx_CH1
OC1
TIMx_CH1N
OC1N
TIMx_CH2
OC2
TIMx_CH2N
OC2N
TIMx_CH3
OC3
TIMx_CH3N
OC3N
OC4
TIMx_CH4
OC5
OC6
MSv40115V3
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