Figure 309. Start Bit Detection When Oversampling By 16 Or 8 - ST STM32WL5 Series Reference Manual

RM0453

Figure 309. Start bit detection when oversampling by 16 or 8

RX state
RX line
Ideal
sample
clock
Real
sample
clock
Conditions
1 1
to validate
the start bit
Falling edge
detection
Note: If the sequence is not complete, the start bit detection aborts and the receiver returns to the
idle state (no flag is set), where it waits for a falling edge.
The start bit is confirmed (RXNE flag set and interrupt generated if RXNEIE = 1, or RXFNE
flag set and interrupt generated if RXFNEIE = 1 if FIFO mode enabled) if the 3 sampled bits
are at '0' (first sampling on the 3rd, 5th and 7th bits finds the 3 bits at '0' and second
sampling on the 8th, 9th and 10th bits also finds the 3 bits at '0').
The start bit is validated but the NE noise flag is set if,
a)
or
b)
If neither of the above conditions are met, the start detection aborts and the receiver returns
to the idle state (no flag is set).
Universal synchronous/asynchronous receiver transmitter (USART/UART)
Idle
1 2 3 4
X X X X
7/16
1 0 X 0 X
At least 2 bits
out of 3 at 0
for both samplings, 2 out of the 3 sampled bits are at '0' (sampling on the 3rd, 5th
and 7th bits and sampling on the 8th, 9th and 10th bits)
for one of the samplings (sampling on the 3rd, 5th and 7th bits or sampling on the
8th, 9th and 10th bits), 2 out of the 3 bits are found at '0'.
5 6 7 8 9
Sampled values
X X X X 9
One-bit time
0 X 0 0 0
At least 2 bits
out of 3 at 0
RM0453 Rev 1
Start bit
10 11 12 13 14 15 16
10 11 12 13 14 15 16
6/16
7/16
0 X X X X X X
ai15471b
1139/1461
1266