Rtc Sub Second Register (Rtc_Ssr); Rtc Initialization Control And Status Register (Rtc_Icsr) - ST STM32WL5 Series Reference Manual

Real-time clock (RTC)
32.6.3

RTC sub second register (RTC_SSR)

Address offset: 0x08
Backup domain reset value: 0x0000 0000
System reset: 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
31 30 29
r r r
15 14 13
r r r
Bits 31:0 SS[31:0]: Synchronous binary counter
32.6.4

RTC initialization control and status register (RTC_ICSR)

This register is write protected. The write access procedure is described in
write protection on page
Address offset: 0x0C
Backup domain reset value: 0x0000 0007
System reset: not affected except INIT, INITF, and RSF bits which are cleared to 0
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res.
1020/1461
28 27 26 25
r r r r
12 11 10 9
r r r r
SS[31:16]: Synchronous binary counter MSB values
When Binary or Mixed mode is selected (BIN = 01 or 10 or 11):
SS[31:16] are the 16 MSB of the SS[31:0] free-running down-counter.
When BCD mode is selected (BIN=00):
SS[31:16] are forced by hardware to 0x0000.
SS[15:0]: Sub second value/Synchronous binary counter LSB values
When Binary mode is selected (BIN = 01 or 10 or 11):
SS[15:0] are the 16 LSB of the SS[31:0] free-running down-counter.
When BCD mode is selected (BIN=00):
SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given
by the formula below:
Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1)
SS can be larger than PREDIV_S only after a shift operation. In that case, the correct
time/date is one second less than as indicated by RTC_TR/RTC_DR.
1007.
28 27 26 25
Res. Res. Res.
12 11 10 9
BCDU[2:0]
rw rw rw rw
24 23 22
SS[31:16]
r r r
8 7 6
SS[15:0]
r r r
24 23 22
Res. Res. Res.
8 7 6
BIN[1:0] INIT INITF
rw rw r
RM0453 Rev 1
21 20 19 18
r r r
5 4 3 2
r r r
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
WUTW
RSF INITS SHPF
F
rc_w0 r r
RM0453
17 16
r r r
1 0
r r r
RTC register
17 16
RECAL
Res.
PF
r
1 0
Res. Res.
r