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Debug support (DBG)
Offset Register name
DP_DLPIDR
(4)
0x04
Reset value
DP_RESENDR
0x08
Reset value
DP_SELECTR
0x08
Reset value
DP_BUFFR
0x0C
Reset value
DP_TARGETSELR
0x0C
Reset value
1. DP_SELECTR.DPBANKSEL = 0.
2. DP_SELECTR.DPBANKSEL = 1.
3. DP_SELECTR.DPBANKSEL = 2.
4. DP_SELECTR.DPBANKSEL = 3.
38.5
Access ports
As shown in
•
AP0, CPU1 (Cortex-M4) access port (AHB-AP): enables access to the debug and trace
features integrated in the core via its internal AHB bus.
•
AP1, CPU2 (Cortex-M0+) access port (AHB-AP): enables access to the debug and
trace features integrated in the core via its internal AHB bus.
The access ports are of MEM-AP type, that is to say the debug and trace component
registers are mapped in the address space of the associated debug bus.
AP is seen by the debugger as a set of 32-bit registers organized in banks of four registers
each. Some of these registers are used to configure or monitor the AP itself, while others
are used to perform a transfer on the bus.
The AP registers are listed in
1342/1461
Table 268. DP register map and reset values (continued)
0
0
0
0
0
0
0
0
0
0
0
0
0
APSEL[3:0]
x
x
x
x
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
x
Figure
385, there are twois one access ports (AP) attached to the DP:
Table 270: AP register map and reset
RESEND[31:0]
0
0
0
0
0
0
0
0
0
RDBUFF[31:0]
0
0
0
0
0
0
0
0
0
TPARTNO[15:0]
x
x
x
x
x
x
x
x
x
RM0453 Rev 1
0
0
0
0
0
0
0
0
0
x
x
x
0
0
0
0
0
0
0
0
0
TDESIGNER[10:0]
x
x
x
x
x
x
x
x
x
values.
RM0453
0
0
0 1
0
0
0
0 0
x
x
x
x
x
0
0
0
0 0
x
x
x
x
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