Gpioh Register Map; Table 74. Gpioh Register Map And Reset Values - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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General-purpose I/Os (GPIO)
Table 73. GPIOC register map and reset values (continued)
Offset Register name
GPIOC_AFRL
0x0820
Reset value
GPIOC_AFRH
0x0824
Reset value
GPIOC_BRR
0x0828
Reset value
Refer to
10.4.36

GPIOH register map

The following table gives the GPIOH register map and reset values.
Offset Register name
GPIOH_MODER
0x1C00
Reset value
GPIOH_OTYPER
0x1C04
Reset value
GPIOH_OSPEEDR
0x1C08
Reset value
GPIOH_PUPDR
0x1C0C
Reset value
GPIOH_IDR
0x1C10
Reset value
GPIOH_ODR
0x1C14
Reset value
GPIOH_BSRR
0x1C18
Reset value
GPIOH_LCKR
0x1C1C
Reset value
GPIOH_AFRL
0x1C20
Reset value
0x1C24
Reserved
426/1461
AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0]
0
0
0
0
AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0]
0
0
0
0
0
0
0
0
Section 2.6: Memory organization

Table 74. GPIOH register map and reset values

0
0
0
0
0
0
0
0
0
0
0
0
0
0
for the register boundary addresses.
0
0
AFSEL3[3:0]
0
Reserved.
RM0453 Rev 1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
RM0453
0
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
0

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