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RM0453
28.7.8
LPTIM counter register (LPTIM_CNT)
Address offset: 0x01C
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 CNT[15:0]: Counter value
When the LPTIM is running with an asynchronous clock, reading the LPTIM_CNT register may
return unreliable values. So in this case it is necessary to perform two consecutive read accesses
and verify that the two returned values are identical.
28.7.9
LPTIM1 option register (LPTIM1_OR)
Address offset: 0x020
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 OR_1: Option register bit 1
0:
LPTIM1 input 2 is connected to I/O
1:
LPTIM1 input 2 is connected to COMP2_OUT
Bit 0 OR_0: Option register bit 0
0:
LPTIM1 input 1 is connected to I/O
1:
LPTIM1 input 1 is connected to COMP1_OUT
28
27
26
25
Res.
Res.
Res.
12
11
10
9
r
r
r
r
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
CNT[15:0]
r
r
r
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0453 Rev 1
Low-power timer (LPTIM)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
r
r
r
r
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
Res.
Res.
1
0
r
r
17
16
Res.
Res.
1
0
OR_1
OR_0
rw
rw
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