ST STM32WL5 Series Reference Manual page 900

General-purpose timer (TIM2)
Table 185. TIM2 register map and reset values (continued)
Register
Offset
name
TIMx_CNT
0x24
Reset value 0
TIMx_PSC
0x28
Reset value
TIMx_ARR
0x2C
Reset value 1
0x30
TIMx_CCR1
0x34
Reset value 0
TIMx_CCR2
0x38
Reset value 0
TIMx_CCR3
0x3C
Reset value 0
TIMx_CCR4
0x40
Reset value 0
0x44
TIMx_DCR
0x48
Reset value
TIMx_DMAR
0x4C
Reset value
TIM2_OR1
0x50
Reset value
TIM2_AF1
0x60
Reset value
900/1461
0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
CNT[30:0]
0 0 0 0 0 0 0 0
0 0
ARR[31:0]
1 1 1 1 1 1 1 1
Reserved
CCR1[31:0]
0 0 0 0 0 0 0 0
CCR2[31:0]
0 0 0 0 0 0 0 0
CCR3[31:0]
0 0 0 0 0 0 0 0
CCR4[31:0]
0 0 0 0 0 0 0 0
Reserved
0 0
ETRSEL
[3:0]
0 0 0 0
RM0453 Rev 1
0 0 0 0 0 0 0 0
PSC[15:0]
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
DBL[4:0]
0 0 0 0 0
DMAB[15:0]
0 0 0 0 0 0 0 0
RM0453
0 0 0 0 0 0
0 0 0 0 0 0
1 1 1 1 1 1
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
DBA[4:0]
0 0 0 0 0
0 0 0 0 0 0
0 0 0