I2C Registers; I2C Control Register 1 (I2C_Cr1) - ST STM32WL5 Series Reference Manual

Inter-integrated circuit (I2C) interface
34.7

I2C registers

Refer to
The peripheral registers are accessed by words (32-bit).
34.7.1

I2C control register 1 (I2C_CR1)

Address offset: 0x00
Reset value: 0x0000 0000
Access: No wait states, except if a write access occurs while a write access to this register is
ongoing. In this case, wait states are inserted in the second write access until the previous
one is completed. The latency of the second write access can be up to
2 x PCLK1 + 6 x I2CCLK.
31 30 29
Res. Res. Res.
15 14 13
RXDMA TXDMA
Res.
EN EN
rw rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 PECEN: PEC enable
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 22 ALERTEN: SMBus alert enable
Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO.
Bit 21 SMBDEN: SMBus device default address enable
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Bit 20 SMBHEN: SMBus host address enable
Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
1110/1461
Section 1.2 on page 58
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
ANF
DNF[3:0]
OFF
rw rw rw rw
0: PEC calculation disabled
1: PEC calculation enabled
Refer to Section 34.3: I2C
0: The SMBus alert pin (SMBA) is not supported in host mode (SMBHEN=1). In device mode
(SMBHEN=0), the SMBA pin is released and the Alert Response Address header is disabled
(0001100x followed by NACK).
1: The SMBus alert pin is supported in host mode (SMBHEN=1). In device mode
(SMBHEN=0), the SMBA pin is driven low and the Alert Response Address header is
enabled (0001100x followed by ACK).
If the SMBus feature is not supported, this bit is reserved and forced by hardware to '0'.
Refer to Section 34.3: I2C
0: Device default address disabled. Address 0b1100001x is NACKed.
1: Device default address enabled. Address 0b1100001x is ACKed.
Refer to Section 34.3: I2C
0: Host address disabled. Address 0b0001000x is NACKed.
1: Host address enabled. Address 0b0001000x is ACKed.
Refer to Section 34.3: I2C
for a list of abbreviations used in register descriptions.
24 23 22
ALERT SMBD
Res. PECEN
EN
rw rw
8 7 6
STOP
ERRIE TCIE
rw rw rw
implementation.
implementation.
implementation.
implementation.
RM0453 Rev 1
21 20 19 18
SMBH WUPE
GCEN
EN EN N
rw rw rw rw
5 4 3 2
NACK ADDR
RXIE
IE IE IE
rw rw rw rw
RM0453
17 16
NOSTR
SBC
ETCH
rw rw
1 0
TXIE PE
rw rw