Fpb Coresight Peripheral Identity Register 2 (Fpb_Pidr2); Fpb Coresight Peripheral Identity Register 3 (Fpb_Pidr3) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Debug support (DBG)
38.9.7

FPB CoreSight peripheral identity register 2 (FPB_PIDR2)

Address offset: 0xFE8
Reset value: 0x0000 002B
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 REVISION[3:0]: component revision number
0x2: r0p3
Bit 3 JEDEC: JEDEC assigned value
0x1: Designer ID specified by JEDEC
Bits 2:0 JEP106ID[6:4]: JEP106 identity code bits [6:4]
0x3: Arm
38.9.8

FPB CoreSight peripheral identity register 3 (FPB_PIDR3)

Address offset: 0xFEC
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 REVAND[3:0]: metal fix version
0x0: No metal fix
Bits 3:0 CMOD[3:0]: customer modified
0x0: No customer modifications
1396/1461
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
®
JEDEC code
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0453 Rev 1
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
REVISION[3:0]
r
r
r
r
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
REVAND[3:0]
r
r
r
r
RM0453
19
18
17
Res.
Res.
Res.
Res.
3
2
1
JEDEC
JEP106ID[6:4]
r
r
r
19
18
17
Res.
Res.
Res.
Res.
3
2
1
CMOD[3:0]
r
r
r
16
0
r
16
0
r

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