Cpu1 Instrumentation Trace Macrocell (Itm) - ST STM32WL5 Series Reference Manual

RM0453
Table 279. CPU1 FPB register map and reset values (continued)
Offset Register name
FPB_REMAPR
0x004
Reset value
FPB_COMP0-7R
0x008 to
0x024
Reset value
0x028 to
Reserved
0xFCC
FPB_PIDR4
0xFD0
Reset value
0xFD4 to
Reserved
0xFDC
FPB_PIDR0
0xFE0
Reset value
FPB_PIDR1
0xFE4
Reset value
FPB_PIDR2
0xFE8
Reset value
FPB_PIDR3
0xFEC
Reset value
FPB_CIDR0
0xFF0
Reset value
FPB_CIDR1
0xFF4
Reset value
FPB_CIDR2
0xFF8
Reset value
FPB_CIDR3
0xFFC
Reset value
Refer to
38.10

CPU1 instrumentation trace macrocell (ITM)

The ITM generates trace information as packets. There are three sources that can generate
packets. If multiple sources generate packets at the same time, the ITM arbitrates the order
in which packets are output. The three sources in decreasing order of priority are:
1 0 0 0 0 0
0 0 0 0 0 0 0
Section 38.8: CPU1 ROM table
REMAP[23:0]
0 0 0 0 0 0 0 0 0
COMP[26:0]
0 0 0 0 0 0 0 0 0
Reserved.
Reserved.
for the register boundary addresses.
RM0453 Rev 1
Debug support (DBG)
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
F4KCOUNT
[3:0]
0 0
0 0
JEP106ID
[3:0]
1 0
REVISION
[3:0]
0 0
REVAND[3:0] CMOD[3:0]
0 0
0 0
CLASS[3:0]
1 1
PREAMBLE[19:12]
0 0
PREAMBLE[27:20]
1 0
0
0 0 0 0 0
JEP106CON
[3:0]
0 0 0 1 0 0
PARTNUM[7:0]
0 0 0 0 1 1
PARTNUM
[11:8]
1 1 0 0 0 0
JEP106ID
[6:4]
1 0 1 0 1 1
0 0 0 0 0 0
PREAMBLE[7:0]
0 0 1 1 0 1
PREAMBLE
[11:8]
1 0 0 0 0 0
0 0 0 1 0 1
1 1 0 0 0 1
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