Figure 339. Transmission Using Dma - ST STM32WL5 Series Reference Manual

RM0453
1. Write the LPUART_TDR register address in the DMA control register to configure it as
the destination of the transfer. The data is moved to this address from memory after
each TXE (or TXFNF if FIFO mode is enabled) event.
2. Write the memory address in the DMA control register to configure it as the source of
the transfer. The data is loaded into the LPUART_TDR register from this memory area
after each TXE (or TXFNF if FIFO mode is enabled) event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA register
5. Configure DMA interrupt generation after half/ full transfer as required by the
application.
6. Clear the TC flag in the LPUART_ISR register by setting the TCCF bit in the
LPUART_ICR register.
7. Activate the channel in the DMA register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector.
In transmission mode, once the DMA has written all the data to be transmitted (the TCIF flag
is set in the DMA_ISR register), the TC flag can be monitored to make sure that the
LPUART communication is complete. This is required to avoid corrupting the last
transmission before disabling the LPUART or entering low-power mode. Software must wait
until TC = 1. The TC flag remains cleared during all data transfers and it is set by hardware
at the end of transmission of the last frame.
Idle preamble
TX line
TXE flag
DMA request
F1
USART_TDR
TC flag
DMA writes
USART_TDR
DMA TCIF flag
(transfer
complete)
Software
DMA writes
configures DMA
F1 into
to send 3 data
USART_TDR
blocks and
enables USART
Note: When FIFO management is enabled, the DMA request is triggered by Transmit FIFO not full
(i.e. TXFNF = 1).
Low-power universal asynchronous receiver transmitter (LPUART)

Figure 339. Transmission using DMA

Frame 1
Set by hardware
cleared by DMA read
F2
Set by hardware
DMA writes DMA writes
F2 into F3 into
USART_TDR USART_TDR
RM0453 Rev 1
Frame 2
Set by hardware
cleared by DMA read
F3
Cleared
by
software
The DMA
transfer is
Software waits until TC=1
complete
(TCIF=1 in
DMA_ISR)
Frame 3
Set by hardware
Ignored by the DMA because
the transfer is complete
ai17192b
Set by
hardware
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