ST STM32WL5 Series Reference Manual page 1382

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Debug support (DBG)
Offset Register name
CTI_APPCLEAR
0x018
Reset value
CTI_APPPULSER
0x01C
Reset value
CTI_INENR0
0x020
Reset value
CTI_INENR1
0x024
Reset value
CTI_INENR2
0x028
Reset value
CTI_INENR3
0x02C
Reset value
CTI_INENR4
0x030
Reset value
CTI_INENR5
0x034
Reset value
CTI_INENR6
0x038
Reset value
CTI_INENR7
0x03C
Reset value
0x040 to
Reserved
0x08C
CTI_OUTENR0
0x0A0
Reset value
CTI_OUTENR1
0x0A4
Reset value
CTI_OUTENR2
0x0A8
Reset value
CTI_OUTENR3
0x0AC
Reset value
CTI_OUTENR4
0x0B0
Reset value
CTI_OUTENR5
0x0B4
Reset value
1382/1461
Table 276. CTI register map and reset values (continued)
Reserved
RM0453 Rev 1
RM0453
APPCLEAR
[3:0]
0
0
0 0
APPPULSE
[3:0]
0
0
0 0
TRIGINEN
[3:0]
0
0
0 0
TRIGINEN
[3:0]
0
0
0 0
TRIGINEN
[3:0]
0
0
0 0
TRIGINEN
[3:0]
0
0
0 0
TRIGINEN
[3:0]
0
0
0 0
TRIGINEN
[3:0]
0
0
0 0
TRIGINEN
[3:0]
0
0
0 0
TRIGINEN
[3:0]
0
0
0 0
TRIGOUTEN
[3:0]
0
0
0 0
TRIGOUTEN
[3:0]
0
0
0 0
TRIGOUTEN
[3:0]
0
0
0 0
TRIGOUTEN
[3:0]
0
0
0 0
TRIGOUTEN
[3:0]
0
0
0 0
TRIGOUTEN
[3:0]
0
0
0 0

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