Tim2 Dma/Interrupt Enable Register (Tim2_Dier); Table 183. Tim2 Internal Trigger Connection - ST STM32WL5 Series Reference Manual

General-purpose timer (TIM2)
Bits 16, 2, 1, 0 SMS[3:0]: Slave mode selection
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
Note: The clock of the slave peripherals (timer, ADC, ...) receiving the TRGO signal must be
Slave TIM
26.4.4

TIM2 DMA/Interrupt enable register (TIM2_DIER)

Address offset: 0x0C
Reset value: 0x0000
15 14 13
Res. Res. Res. CC4DE CC3DE CC2DE CC1DE
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 Reserved, must be kept at reset value.
Bit 12 CC4DE: Capture/Compare 4 DMA request enable
Bit 11 CC3DE: Capture/Compare 3 DMA request enable
880/1461
When external signals are selected the active edge of the trigger signal (TRGI) is linked to
the polarity selected on the external input (see Input Control register and Control Register
description.
0000: Slave mode disabled - if CEN = '1 then the prescaler is clocked directly by the internal
clock.
0001: Encoder mode 1 - Counter counts up/down on TI1FP1 edge depending on TI2FP2
level.
0010: Encoder mode 2 - Counter counts up/down on TI2FP2 edge depending on TI1FP1
level.
0011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
0100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter
and generates an update of the registers.
0101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of
the counter are controlled.
0110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
0111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
1000: Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)
reinitializes the counter, generates an update of the registers and starts the counter.
(TS=00100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.
enabled prior to receive events from the master timer, and the clock frequency
(prescaler) must not be changed on-the-fly while triggers are received from the master
timer.

Table 183. TIM2 internal trigger connection

TIM2
12 11 10 9
rw rw rw rw
0: CC4 DMA request disabled.
1: CC4 DMA request enabled.
0: CC3 DMA request disabled.
1: CC3 DMA request enabled.
ITR0
TIM1
8 7 6
UDE Res. TIE
rw rw
RM0453 Rev 1
ITR1 ITR2 - ITR8
-
5 4 3 2
Res. CC4IE CC3IE CC2IE
rw rw rw
RM0453
-
1 0
CC1IE UIE
rw rw