Itm Stimulus Register X (Itm_Stimrx); Itm Trace Enable Register (Itm_Ter) - ST STM32WL5 Series Reference Manual

Debug support (DBG)
1. Software trace
Software can write directly to any of 32 x 32-bit ITM stimulus registers to generate
packets. The permission level for each port can be programmed. When software writes
to an enabled stimulus port, the ITM combines the identity of the port, the size of the
write access and the data written, into a packet that it writes to a FIFO. The ITM outputs
packets from the FIFO onto the trace bus. Reading a stimulus port register returns the
status of the stimulus register (empty or pending) in bit 0.
2. Hardware trace
The DWT generates trace packets in response to a data trace event, a PC sample or a
performance profiling counter wraparound. The ITM outputs these packets on the trace
bus.
3. Local timestamping
The ITM contains a 21-bit counter clocked by the (pre-divided) processor clock. The
counter value is output in a timestamp packet on the trace bus. The counter is reset to
zero every time a timestamp packet is generated. The timestamps thus indicate the
time elapsed since the previous timestamp packet.
38.10.1

ITM stimulus register x (ITM_STIMRx)

Address offset: 0x000 + 0x004 * x, (x = 0 to 31)
Reset value: 0xXXXX XXXX
31 30 29
r r r
15 14 13
r r r
Bits 31:0 STIMULUS[31:0]: Write data is output on the trace bus as a software event packet.
When reading, bit 0 is a FIFOREADY indicator:
0: Stimulus port buffer is full (or port is disabled).
1: Stimulus port can accept new write data.
38.10.2

ITM trace enable register (ITM_TER)

Address offset: 0x080
Reset value: 0x0000 0000
31 30 29
r r r
15 14 13
r r r
1400/1461
28 27 26 25
r r r r
12 11 10 9
r r r r
28 27 26 25
r r r r
12 11 10 9
r r r r
24 23 22
STIMULUS[31:16]
r r r
8 7 6
STIMULUS[15:0]
r r r
24 23 22
STIMENA[31:16]
r r r
8 7 6
STIMENA[15:0]
r r r
RM0453 Rev 1
21 20 19 18
r r r r
5 4 3 2
r r r r
21 20 19 18
r r r r
5 4 3 2
r r r r
RM0453
17 16
r r
1 0
r r
17 16
r r
1 0
r r