Rs232 Hardware Flow Control And Rs485 Driver Enable; Figure 326. Reception Using Dma; Figure 327. Hardware Flow Control Between 2 Usarts - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Table of Contents

Universal synchronous/asynchronous receiver transmitter (USART/UART)

DMA TCIF flag

(transfer complete)

Software configures the

DMA to receive 3 data

blocks and enables

When FIFO management is enabled, the DMA request is triggered by Receive FIFO not

empty (i.e. RXFNE = 1).

Error flagging and interrupt generation in multibuffer communication

If any error occurs during a transaction in multibuffer communication mode, the error flag is

asserted after the current byte. An interrupt is generated if the interrupt enable flag is set.

For framing error, overrun error and noise flag which are asserted with RXNE (RXFNE in

case FIFO mode is enabled) in single byte reception, there is a separate error flag interrupt

enable bit (EIE bit in the USART_CR3 register), which, if set, enables an interrupt after the

current byte if any of these errors occur.

RS232 Hardware flow control and RS485 Driver Enable

It is possible to control the serial data flow between 2 devices by using the nCTS input and

the nRTS output. The

Set by hardware

cleared by DMA read

DMA reads F1

from USART_RDR

shows how to connect 2 devices in this mode:

RM0453 Rev 1

DMA reads F2

DMA reads F3

from USART_RDR

Set by hardware

The DMA transfer

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