Figure 369. Msb Justified 16-Bit Or 32-Bit Full-Accuracy Length; Figure 370. Msb Justified 24-Bit Frame Length - ST STM32WL5 Series Reference Manual

Serial peripheral interface / integrated interchip sound (SPI/I2S)
For transmission, each time an MSB is written to SPIx_DR, the TXE flag is set and its
interrupt, if allowed, is generated to load the SPIx_DR register with the new value to send.
This takes place even if 0x0000 have not yet been sent because it is done by hardware.
For reception, the RXNE flag is set and its interrupt, if allowed, is generated when the first
16 MSB half-word is received.
In this way, more time is provided between two write or read operations, which prevents
underrun or overrun conditions (depending on the direction of the data transfer).
MSB justified standard
For this standard, the WS signal is generated at the same time as the first data bit, which is
the MSBit.
Data are latched on the falling edge of CK (for transmitter) and are read on the rising edge
(for the receiver).
CK
WS
SD
1298/1461

Figure 369. MSB Justified 16-bit or 32-bit full-accuracy length

CK
Transmission
WS
SD
MSB

Figure 370. MSB justified 24-bit frame length

Transmission
24 bit data
LSB
MSB
Channel left 32-bit
RM0453 Rev 1
Reception
16- or 32 bit data
LSB MSB
Channel left
Reception
8-bit remaining
0 forced
Channel right
Channel right
RM0453
MS30100 V1
MS30101V1