Debug Support (Dbg); Dbg Introduction And Main Features - ST STM32WL5 Series Reference Manual

Debug support (DBG)

38 Debug support (DBG)
38.1

DBG introduction and main features

A comprehensive set of debug features is provided to support software development and
system integration:
•
Independent breakpoint debugging of each CPU core in the system
•
Code execution tracing
•
Software instrumentation
• Cross-triggering
The debug features can be controlled via a JTAG/Serial-wire debug access port, using
industry standard debugging tools. A trace port allows data to be captured for logging and
analysis.
The debug features are based on Arm CoreSight™ components.
•
General features:
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• CPU1 debug features
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•
CPU2 debug features:
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CPU1 debug features are accessible by the debugger via the CPU1 AHB-AP.
CPU2 debug features are accessible by the debugger via the CPU2 AHB-AP and its
associated AHB bus.
Additional information can be found in the Arm
Device level debug features are controlled in the DBGMCU (see
accessible by the CPU1.
1324/1461
SWJ-DP: JTAG/Serial-wire debug port
AHB-AP: AHB access port
ROM table (see Section
System control space (SCS)
Breakpoint unit (FPB) (see
Data watchpoint and trace unit (DWT) (see
Instrumentation trace macrocell (ITM) (see
Trace port interface unit (TPIU) (see
Cross trigger interface (CTI) (see
ROM tables (see Section
System control space (SCS)
Breakpoint unit (BPU) (see
Data watchpoint and trace unit (DWT) (see
Cross trigger interface (CTI) (see
38.8)
Section 38.9)
Section
Section
Section
Section 38.7)
38.13)
Section 38.14)
Section
Section 38.7)
®
documents referenced in
RM0453 Rev 1
38.6)
38.10)
38.11)
38.6)
Section
Section 38.12), only
RM0453
38.15.