Programmable Sampling Time (Smpx[2:0]) - ST STM32WL5 Series Reference Manual

RM0453
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Sequencer fully configurable
The CHSELRMOD bit is set in ADC_CFGR1 register.
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After programming ADC CHSELR, SCANDIR and CHSELRMOD bits, it is mandatory to wait
for CCRDY flag before starting conversions. It indicates that the new channel setting has
been applied. If a new configuration is required, the CCRDY flag must be cleared prior to
starting the conversion.
The software is allowed to program the CHSEL, SCANDIR, CHSELRMOD bits only when
ADSTART bit is cleared to 0 (which ensures that no conversion is ongoing).
Temperature sensor, DAC output, V
The temperature sensor is connected to channel ADC V
The internal voltage reference V
The V
BAT
The internal dac_out1 output voltage is connected to ADC V
18.3.9

Programmable sampling time (SMPx[2:0])

Before starting a conversion, the ADC needs to establish a direct connection between the
voltage source to be measured and the embedded sampling capacitor of the ADC. This
sampling time must be enough for the input voltage source to charge the sample and hold
capacitor to the input voltage level.
Having a programmable sampling time allows the conversion speed to be trimmed
according to the input resistance of the input voltage source.
The ADC samples the input voltage for a number of ADC clock cycles that can be modified
using the SMP1[2:0] and SMP2[2:0] bits in the ADC_SMPR register.
Each channel can choose one out of two sampling times configured in SMP1[2:0] and
SMP2[2:0] bitfields, through SMPSELx bits in ADC_SMPR register.
The total conversion time is calculated as follows:
t
CONV
Example:
With ADC_CLK = 16 MHz and a sampling time of 1.5 ADC clock cycles:
t
CONV
The ADC indicates the end of the sampling phase by setting the EOSMP flag.
Any channel can belong to in these sequences
Sequencer length is up to 8 channels
The order in which the channels are scanned is independent from the channel
number. Any order can be configured through SQ1[3:0] to SQ8[3:0] bits in
ADC_CHSELR register.
Only channel 0 to channel 14 can be selected in this sequence
If the sequencer detects SQx[3:0] = 0b1111, the following SQx[3:0] registers are
ignored.
If no 0b1111 is programmed in SQx[3:0], the sequencer scans full eight channels.
channel is connected to ADC V
= Sampling time + 12.5 x ADC clock cycles
= 1.5 + 12.5 = 14 ADC clock cycles = 0.875 µs
and V
REFINT
is connected to channel ADC V
REFINT
[14] channel.
IN
RM0453 Rev 1
Analog-to-digital converter (ADC)
internal channels
BAT
[12].
IN
[13].
IN
[17] channel.
IN
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