Table of Contents
Advertisement
Debug support (DBG)
38.8.8
CPU1 ROM CoreSight peripheral identity register 1 (ROM_CIDR1)
Address offset: 0xFF4
Reset value: 0x0000 0010
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 CLASS[3:0]: component ID bits [15:12] - component class
0x1: ROM table component
Bits 3:0 PREAMBLE[11:8]: component ID bits [11:8]
0x0: Common ID value
38.8.9
CPU1 ROM CoreSight component identity register 2 (ROM_CIDR2)
Address offset: 0xFF8
Reset value: 0x0000 0005
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PREAMBLE[19:12]: component ID bits [23:16]
0x05: Common ID value
1390/1461
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0453 Rev 1
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
CLASS[3:0]
r
r
r
r
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
PREAMBLE[19:12]
r
r
r
r
RM0453
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
PREAMBLE[11:8]
r
r
r
r
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
r
r
r
r
Advertisement
Table of Contents
Need help?
Do you have a question about the STM32WL5 Series and is the answer not in the manual?
Questions and answers