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RM0453
38.8.2
CPU1 ROM CoreSight peripheral identity register 4 (ROM_PIDR4)
Address offset: 0xFD0
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:4 F4KCOUNT[3:0]: register file size
0x0: Register file occupies a single 4-Kbyte region.
Bits 3:0 JEP106CON[3:0]: JEP106 continuation code
0x0: STMicroelectronics JEDEC continuation code
38.8.3
CPU1 ROM CoreSight peripheral identity register 0 (ROM_PIDR0)
Address offset: 0xFE0
Reset value: 0x0000 0097
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 PARTNUM[7:0]: part number bits [7:0]
0x97: STM32WL5x
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
27
26
25
24
Res.
Res.
Res.
Res.
11
10
9
8
Res.
Res.
Res.
Res.
RM0453 Rev 1
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
F4KCOUNT[3:0]
r
r
r
r
23
22
21
20
Res.
Res.
Res.
Res.
7
6
5
4
PARTNUM[7:0]
r
r
r
r
Debug support (DBG)
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
JEP106CON[3:0]
r
r
r
r
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
r
r
r
r
1387/1461
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