ST STM32WL5 Series Reference Manual page 1204

Universal synchronous/asynchronous receiver transmitter (USART/UART)
Bits 31:26 Reserved, must be kept at reset value.
Bit 25 TCBGT: Transmission complete before guard time flag
Note: If the USART does not support the Smartcard mode, this bit is reserved and kept at
Bits 24:23 Reserved, must be kept at reset value.
Bit 22 REACK: Receive enable acknowledge flag
Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and
Bit 21 TEACK: Transmit enable acknowledge flag
Bit 20 WUF: Wakeup from low-power mode flag
Note: When UESM is cleared, WUF flag is also cleared.
Bit 19 RWU: Receiver wakeup from Mute mode
Note: If the USART does not support the wakeup from Stop feature, this bit is reserved and
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This bit is set when the last data written in the USART_TDR has been transmitted correctly
out of the shift register.
It is set by hardware in Smartcard mode, if the transmission of a frame containing data is
complete and if the smartcard did not send back any NACK. An interrupt is generated if
TCBGTIE = 1 in the USART_CR3 register.
This bit is cleared by software, by writing 1 to the TCBGTCF in the USART_ICR register or
by a write to the USART_TDR register.
0: Transmission is not complete or transmission is complete unsuccessfully (i.e. a NACK is
received from the card)
1: Transmission is complete successfully (before Guard time completion and there is no
NACK from the smart card).
reset value. If the USART supports the Smartcard mode and the Smartcard mode is
enabled, the TCBGT reset value is '1'. Refer to
on page 1129.
This bit is set/reset by hardware, when the Receive Enable value is taken into account by
the USART.
It can be used to verify that the USART is ready for reception before entering low-power
mode.
kept at reset value. Refer to
This bit is set/reset by hardware, when the Transmit Enable value is taken into account by
the USART.
It can be used when an idle frame request is generated by writing TE = 0, followed by
TE = 1 in the USART_CR1 register, in order to respect the TE = 0 minimum period.
This bit is set by hardware, when a wakeup event is detected. The event is defined by the
WUS bitfield. It is cleared by software, writing a 1 to the WUCF in the USART_ICR register.
An interrupt is generated if WUFIE = 1 in the USART_CR3 register.
If the USART does not support the wakeup from Stop feature, this bit is reserved and
kept at reset value. Refer to
This bit indicates if the USART is in Mute mode. It is cleared/set by hardware when a
wakeup/mute sequence is recognized. The Mute mode control sequence (address or IDLE)
is selected by the WAKE bit in the USART_CR1 register.
When wakeup on IDLE mode is selected, this bit can only be set by software, writing 1 to the
MMRQ bit in the USART_RQR register.
0: Receiver in active mode
1: Receiver in Mute mode
kept at reset value. Refer to
Section 35.4: USART implementation on page
Section 35.4: USART implementation on page
Section 35.4: USART implementation on page
RM0453 Rev 1
Section 35.4: USART implementation
RM0453
1129.
1129.
1129.