Figure 299. Transfer Sequence Flowchart For Smbus Slave Transmitter N Bytes + Pec; Figure 300. Transfer Bus Diagrams For Smbus Slave Transmitter (Sbc=1) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution
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Inter-integrated circuit (I2C) interface
Caution:
The PECBYTE bit has no effect when the RELOAD bit is set.

Figure 299. Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC

Figure 300. Transfer bus diagrams for SMBus slave transmitter (SBC=1)

Example SMBus slave transmitter 2 bytes + PEC,
NBYTES
EV1: ADDR ISR: check ADDCODE, program NBYTES=3, set PECBYTE, set ADDRCF
EV2: TXIS ISR: wr data1
EV3: TXIS ISR: wr data2
1098/1461
No
Read ADDCODE and DIR in I2C_ISR
I2C_CR2.NBYTES = N + 1
Write I2C_TXDR.TXDATA
ADDR
TXIS TXIS
S
Address
A
data1
EV1
EV2
EV3
SMBus slave
transmission
Slave initialization
I2C_ISR.ADDR =
1?
Yes
PECBYTE=1
Set I2C_ICR.ADDRCF
No
I2C_ISR.TXIS
=1?
Yes
A
data2
A
PEC
3
RM0453 Rev 1
SCL
stretched
MS19867V2
legend:
transmission
reception
SCL stretch
NA
P
RM0453
MS19869V2

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