Syscfg Cpu2 Interrupt Mask Register 2 (Syscfg_C2Imr2) - ST STM32WL5 Series Reference Manual

System configuration controller (SYSCFG)
Bit 5 RCCIM: RCC interrupt mask to CPU2
0: RCC interrupt forwarded to CPU2
1. RCC interrupt to CPU2 masked
Bit 4 Reserved, must be kept at reset value.
Bit 3 RTCWKUPIM: RTCWKUP interrupt mask to CPU2
0: RTCWKUP interrupt forwarded to CPU2
1. RTCWKUP interrupt to CPU2 masked
Bit 2 RTCSSRUIM: RTC SSRU interrupt mask to CPU2
0: RTC SSRU interrupt forwarded to CPU2
1. RTC SSRU interrupt to CPU2 masked
Bit 1 RTCALARMIM: RTCALARM interrupt mask to CPU2
0: RTCALARM interrupt forwarded to CPU2
1. RTCALARM interrupt to CPU2 masked
Bit 0 RTCSTAMPTAMPLSECSSIM: RTCSTAMPTAMPLSECSS interrupt mask to CPU2
0: RTCSTAMPTAMPLSECSS interrupt forwarded to CPU2
1. RTCSTAMPTAMPLSECSS interrupt to CPU2 masked
11.2.14

SYSCFG CPU2 interrupt mask register 2 (SYSCFG_C2IMR2)

Address offset: 0x10C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:21 Reserved, must be kept at reset value.
Bit 20 PVDIM: PVD interrupt mask to CPU2
0: PVD interrupt forwarded to CPU2
1. PVD interrupt to CPU2 masked
Bit 19 Reserved, must be kept at reset value.
Bit 18 PVM3IM: PVM3 interrupt mask to CPU2
0: PVM3 interrupt forwarded to CPU2
1. PVM3 interrupt to CPU2 masked.
Bits 17:16 Reserved, must be kept at reset value.
Bit 15 DMAMUX1IM: DMAMUX1 interrupt mask to CPU2
0: DMAMUX1 interrupt forwarded to CPU2
1. DMAMUX1 interrupt to CPU2 masked
442/1461
28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
Res.
rw rw
RM0453 Rev 1
21 20 19 18
Res. PVDIM Res.
rw rw
5 4 3 2
rw rw rw rw
RM0453
17 16
Res. Res.
1 0
rw rw