Figure 359. Master Full-Duplex Communication In Packed Mode - ST STM32WL5 Series Reference Manual

RM0453

Figure 359. Master full-duplex communication in packed mode

NSS
SCK
BSY
MOSI
SPE
TXE
DTx1-2
FTLVL
00
MISO
1
RXNE
DMA or software control at Rx events
FRLVL
Assumptions for master full-duplex communication in packed mode example:
• Data size = 5 bit
•
Read/write FIFO is performed mostly by 16-bit access
• FRXTH=0
If DMA is used:
•
Number of Tx frames to be transacted by DMA is set to 3
•
Number of Rx frames to be transacted by DMA is set to 3
•
PSIZE for both Tx and Rx DMA channel is set to 16-bit
•
LDMA_TX=1 and LDMA_RX=1
See also
and notes.
Serial peripheral interface / integrated interchip sound (SPI/I2S)
DTx1-2
5 4 3 2 1 5
3
Enable Tx/Rx DMA or interrupts
DTx3-4
10 11 10
4
5 4 3 2 1 5 4 3 2
DRx1-2
00
DMA Tx TICF
: Communication diagrams on page 1283
2
DTx3-4
4 3 2 1 5 4 3 2 1 5 4 3 2 1
3
DTx5
DMA or software control at Tx events
7
11 10 01
1 5 4 3 2 1 5 4 3 2
DRx3-4
DRx3-4
DRx1-2
01 10 00 01
DMA Rx TICF
5
for details about common assumptions
RM0453 Rev 1
DTx5
5 4 3 2 1
00
1 5 4 3 2 1
DRx5
FRTHX=1
DRx5
8
00 01
10
1
00
MSv32125V2
1287/1461
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