Usart Functional Description; Usart Block Diagram; Figure 305. Usart Block Diagram - ST STM32WL5 Series Reference Manual

Universal synchronous/asynchronous receiver transmitter (USART/UART)
35.5

USART functional description

35.5.1

USART block diagram

usart_wkup
usart_tx_dma
usart_rx_dma
usart_pclk
usart_ker_ck
The simplified block diagram given in
domains:
•
The usart_pclk clock domain
The usart_pclk clock signal feeds the peripheral bus interface. It must be active when
accesses to the USART registers are required.
•
The usart_ker_ck kernel clock domain.
The usart_ker_ck is the USART clock source. It is independent from usart_pclk and
delivered by the RCC. The USART registers can consequently be written/read even
when the usart_ker_ck clock is stopped.
When the dual clock domain feature is disabled, the usart_ker_ck clock is the same as
the usart_pclk clock.
There is no constraint between usart_pclk and usart_ker_ck: usart_ker_ck can be faster
or slower than usart_pclk. The only limitation is the software ability to manage the
communication fast enough.
When the USART operates in SPI slave mode, it handles data flow using the serial interface
clock derived from the external SCLK signal provided by the external master SPI device.
The usart_ker_ck clock must be at least 3 times faster than the clock on the CK input.
1130/1461

Figure 305. USART block diagram

IRQ Interface
usart_it
DMA Interface
COM Controller
USART_CR1
USART_ISR
USART_CR2
USART_CR3
USART_RQR
USART_ICR
USART_TDR
USART_RDR
USART_
RTOR
USART_GTPR
USART_BRR
USART_
PRESC
usart_ker_ck clock domain
usart_pclk
clock domain
usart_ker_ck_pres
Figure 305 shows two fully-independent clock
RM0453 Rev 1
USART
Hardware
flow control
TX Shift Reg
...
RX Shift Reg
...
Baudrate
generator &
orversampling
RM0453
CK
CTS/NSS
RTS/DE
TX
RX
MSv40854V3