Lpuart Register Map; Table 254. Lpuart Register Map And Reset Values - ST STM32WL5 Series Reference Manual

RM0453
36.7.13

LPUART register map

The table below gives the LPUART register map and reset values.
Register
Offset
name
LPUART_CR1
FIFO mode
0x00
enabled
Reset value 0
LPUART_CR1
FIFO mode
0x00
disabled
Reset value
LPUART_CR2
0x04
Reset value 0
LPUART_CR3
0x08
Reset value 0
LPUART_BRR
0x0C
Reset value
0x10-
0x14
LPUART_RQR
0x18
Reset value
LPUART_ISR
FIFO mode
0x1C
enabled
Reset value
LPUART_ISR
FIFO mode
0x1C
disabled
Reset value
LPUART_ICR
0x20
Reset value
LPUART_RDR
0x24
Reset value
LPUART_TDR
0x28
Reset value
Low-power universal asynchronous receiver transmitter (LPUART)

Table 254. LPUART register map and reset values

DEAT[4:0]
0 0 0 0 0 0 0
DEAT[4:0]
0 0 0 0 0 0
ADD[7:0]
0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
0 0 0 1 0
0
DEDT[4:0]
0 0 0 0 0 0 0
DEDT[4:0]
0 0 0 0 0 0 0
0 0 0 0 0
WUS
[1:0]
0 0 0 0
0
Reserved
0 0 0 0 0 0
0 0 0 0 0 0
0 0
RM0453 Rev 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
STOP
[1:0]
0 0
0 0 0 0 0 0 0
BRR[19:0]
0 0 0 0 0 0 0 0
0 0 1 1
0 0 1 1
0 0
0 0 0
0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0
0 0
0 0 0 0 0 0
0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0
RDR[8:0]
0 0 0 0 0 0
TDR[8:0]
0 0 0 0 0 0
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